This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-186341, filed Jun. 30, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a field effect transistor, and more particularly to a technique of allowing a field effect transistor having a Double RESURF (Reduced Surface Field) structure to realize a high breakdown voltage.
As a FET (Field Effect Transistor) employing a MOS (Metal Oxide Semiconductor) structure, there is a known device that has a so-called Double RESURF structure wherein a drift layer is formed in the surface of a semiconductor active layer, and a RESURF layer is formed in the surface of the drift layer. For example, an N-MOSFET is fabricated to have an active layer and a RESURF layer, both of which are the p-type, and a drift layer of the n-type. In the MOSFET having such a structure, the n-drift layer is sandwiched by the p-RESURF layer and the p-active layer on the upper and lower sides, respectively, and thus can be easily depleted. Accordingly, the drift layer can be doped with an n-carrier impurity at a higher dose, thereby providing an advantage in that the ON-resistance decreases.
FIG. 21 is a sectional view showing a conventional N-MOSFET having a Double RESURF structure. As shown in FIG. 21, in the surface -of a p-semiconductor active layer 61, an n-drift layer 63 and a p-base layer 65 are formed to be adjacent to each other. An n+-drain layer 67 and a p-RESURF layer 69 are formed in the surface of the drift layer 63. An n+-source layer 71 and a p+-contact layer 73 are formed to be adjacent to each other in the surface of the base layer 65. A gate electrode 76 is arranged through a gate insulating film on that region of the base layer 65, which is located between the drift layer 63 and the source layer 71.
The RESURF layer 69 is arranged in the surface of the drift layer 63 such that it is located between the base layer 65 and the drain layer 67 with gaps relative to the layers 65 and 67 in a direction in which electrons drift. FIG. 22 is a graph showing the profiles of the impurity dose in the drift layer 63 and the RESURF layer 69, corresponding to a region XXIIxe2x80x94XXII in FIG. 21. As shown in FIG. 22, each of the RESURF layer 69 and the drift layer 63 is doped with an impurity at a dose substantially uniform from the base layer 65 side to the drain layer 67 side.
According to research conducted by the present inventors, a problem has been found in the MOSFET shown in FIG. 21, in that an electric field is concentrated at the end of the drain layer 67 on the RESURF layer 69 side during the OFF state, and thus it is difficult to obtain a high breakdown voltage. It is thought that a reason for this is that the Double RESURF structure allows the drift layer 63 to be very easily depleted, whereby the electric field is concentrated near the end of the drain layer 67 having a high carrier impurity concentration
The present invention has been made in consideration of the problem of the prior art, and its object is to provide a field effect transistor having a Double RESURF structure, which can not only reduce the resistance in an ON state, i.e., realize a low ON-resistance, but also increase the breakdown voltage in an OFF state, i.e., realize a high breakdown voltage.
According to a first aspect of the present invention, there is provided a field effect transistor comprising:
a semiconductor active layer of a second conductivity type;
a drift layer of a first conductivity type and a base layer of the second conductivity type, which are selectively formed in a surface of the active layer;
a drain layer of the first conductivity type formed in a surface of the drift layer:
a source layer of the first conductivity type formed in a surface of the base layer and separated from the drift layer;
an electric-field-relaxing layer of the second conductivity type formed in the surface of the drift layer and located between the base layer and the drain layer;
a gate electrode arranged through a gate insulating film on a region of the base layer, which is located between the drift layer and the source layer; and
drain and source electrodes electrically connected to the drain and source layers, respectively,
wherein the electric-field-relaxing layer comprises a region doped with a carrier impurity of the second conductivity type at a dose that is set to be lower on the drain layer side than on the base layer side.
According to a second aspect of the present invention, there is provided a field effect transistor comprising:
a semiconductor active layer of a second conductivity type;
a drift layer of a first conductivity type and a base layer of the second conductivity type, which are selectively formed in a surface of the active layer;
a drain layer of the first conductivity type formed in a surface of the drift layer:
a source layer of the first conductivity type formed in a surface of the base layer and separated from the drift layer;
an electric-field-relaxing layer of the second conductivity type formed in the surface of the drift layer and located between the base layer and the drain layer;
a gate electrode arranged through a gate insulating film on a region of the base layer, which is located between the drift layer and the source layer; and
drain and source electrodes electrically connected to the drain and source layers, respectively,
wherein the drift layer comprises a region doped with a carrier impurity of the first conductivity type at a dose that is set to be lower on the base layer side than on the drain layer side.
According to a third aspect of the present invention, there is provided a field effect transistor comprising:
a semiconductor active layer of a first conductivity type;
a drift layer of the first conductivity type and a base layer of a second conductivity type, which are selectively formed in a surface of the active layer;
a drain layer of the first conductivity type formed in a surface of the drift layer:
a source layer of the first conductivity type formed in a surface of the base layer and separated from the drift layer;
an electric-field-relaxing layer of the second conductivity type sandwiched between the drift layer and the active layer and located between the base layer and the drain layer;
a gate electrode arranged through a gate insulating film on a region of the base layer, which is located between the drift layer and the source layer; and
drain and source electrodes electrically connected to the drain and source layers, respectively,
wherein the electric-field-relaxing layer comprises a region doped with a carrier impurity of the second conductivity type at a dose that is set to be lower on the drain layer side than on the base layer side.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.